The present application relates to thin film structures and processes for making the same. More particularly, the present concepts relate to a thin film transistor where the source and drain contacts are formed so as not to overlap the transistor gate, thereby reducing or eliminating parasitic capacitance and feed-through voltage.
Aspects of the present application may be useful to the manufacture of thin film transistors with lowered parasitic capacitance between the drain and source contacts and the gate contact, and more particularly to the manufacture of such TFTs using additive printing processes. Such TFTs may be used in electronic devices and/or components such as but not limited to low cost display backplanes.
Additive printing, additive processing or other similar terminology refers to processes in which materials are arranged and formed into electronic components without subsequent material removal steps. This is in contrast to typical semi-conductor fabrication methods which require deposition of material followed by selected removal of portions of the material using techniques such as photolithography, chemical and/or vapor etching, or other subtractive manufacturing techniques.
Additive printing of active materials is considered a desirable process to fabricate devices, since it is cost effective, where each material is deposited where it needs to be in a single process step, and the only wasted material is the solvent.
Among the issues in TFT manufacturing, for both additive and subtractive processing, is the need reduce or eliminate TFT parasitic capacitance, which arises from the overlap of the source and drain contacts with the gate contact. The existence of this parasitic capacitance results in a variety of negative issues, including not allowing electronic displays to operate at high refresh rates.
A number of proposals to provide TFT self-alignment to remove overlap between the source-drain contacts and the gate contact have been proposed in connection with manufacturing of TFTs using subtractive manufacturing processes. For example, U.S. Pat. No. 6,017,641, entitled “Thin Film Transistor With Reduced Parasitic Capacitance and Reduced Feedthrough Voltage,” to Mei et al., issued Aug. 22, 2000; and U.S. Pat. No. 5,717,223, entitled “Array With Amorphous Silicon TFTs In Which Channel Leads Overlap Insulating Region No More Than Maximum Overlap,” to Hack et al., issued Feb. 10, 1998, among others.
While there is an issue of parasitic capacitance in connection with TFTs designed using subtractive processing techniques, it is a particular issue with additive printing processing techniques. This is true since additive printing is not able to register layers to the precision that is possible with lithography, as used in the subtractive domain. Thus it is necessary in additive printing to provide a relatively large contact overlap, which in turn increases TFT parasitic capacitance.